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Ordering number : ENN8011A
LC723781N LC723782N LC723783N LC723784 LC723785
Overview
CMOS IC
Electronic tuning system for car audio
ETR Microcontrollers
The LC723780 Series are large-capacity ETR microcontrollers that can support up to 128KB of ROM and up to 8KB of RAM. In addition to the expanded table reference instruction to support large-capacity program ROM, the LC723780 Series provide enhanced interrupt capability to directly control CD mechanism and CD-DSP, and the capability to support the RDS models. They also have a built-in serial I/O port and an 8-input 8-bit A/D converter for communicating with the internal and external devices, and for minimizing the connecting wire between the front panel board and the main board, particularly for car audio systems. The on-chip high-performance PLL circuit provides a high-speed lock circuit used to search for alternative frequencies of RDS in a short time, the ability to control the C/N characteristics of a local oscillator, and the high S/N through the direct PLL configuration.
Functions
* ROM * RAM : Up to 64K steps (65,535x16-bits) The subroutine area holds 4K steps (4,096x16-bits) : Up to 16Kx4-bits (In banks 00 through FF) LC723781N-ROM : 40KB, RAM : 2KB LC723782N-ROM : 48KB, RAM : 2KB LC723783N-ROM : 64KB, RAM : 4KB LC723784-ROM : 96KB, RAM : 6KB LC723785-ROM : 128KB, RAM : 8KB : 32levels
* Stack
Any and all SANYO Semiconductor products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO Semiconductor representative nearest you before using any SANYO Semiconductor products described or contained herein in such applications. SANYO Semiconductor assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor products described or contained herein.
92706 / 80505HKIM B8-9065,9068,9069,8420,8219 / 91004JOIM No.8011-1/14
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* Serial I/O : Three channels. These circuits can support both 2-wire and 3-wire 8-bit communication techniques, and can be switched between MSB first and LSB first operation. One of six internally generated serial transfer clock rates can be selected: 12.5kHz, 37.5kHz, 187.5kHz, 281.25kHz, 375kHz, and 450kHz : Seven interrupt inputs (pins INT0 through INT5, and the HOLD pin) These interrupts can be set to switch between rising and falling edges, although the HOLD pin only supports falling edge detection. : Seven interrupts ; four internal timer interrupts, and three serial I/O interrupts.
* External interrupts * Internal interrupts
Functions (Continued)
: 16 levels Interrupts are prioritized in hardware as follows : HOLD pin>INT0 pin>INT1 pin>INT2 pin>INT3 pin>INT4 pin>INT5 pin> S-I/O0>S-I/O1>S-I/O2>Internal TMR0>Internal TMR1>Internal TMR2> Internal TMR3 * A/D Converter : 8-bit resolution and 8 inputs * General-purpose ports : Input ports : 13 Output ports : 4 I/O ports : 62 (These pins can be switched between input and output in 1-bit units.) * PLL block : Includes a sub-charge pump for high-speed locking. Supports dead zone control. Built-in unlock detection circuit Twelve reference frequencies : 1kHz, 3kHz, 3.125kHz, 5kHz, 6.25kHz, 9kHz, 10kHz, 12.5kHz, 25kHz, 30kHz, 50kHz, and 100kHz * Universal counter : This 20-bit counter can be used for either frequency or period measurement and supports four measurement (calculation) periods : 1ms, 4ms, 8ms, and 32ms * Timers : Two fixed timers and two programmable timers (8-bit counters) TMR0 : Supports four periods : 10s, 100s, 1ms, and 5ms TMR1 : Supports four periods : 10s, 100s, 1ms, and 10ms TMR2 and TMR3 : Programmable 8-bit counters. Input clocks with 10s, 100s, and 1ms One 125-ms timer flip-flop provided * Beep circuit : Provides 12 fixed beep tones : 500Hz, 1kHz, 2kHz, 2.08kHz, 2.2kHz, 2.5kHz, 3kHz, 3.125kHz, 3.33kHz, 3.75kHz, 4.17kHz, and 7.03kHz Programmable 8-bit beep tone generator. Reference clocks with frequencies of 50kHz, 15kHz, and 5kHz. * Reset : Built-in voltage detection reset circuit External reset pin * Cycle time : 1.33s/833ns (All instructions are one word), X'tal : 4.5MHz/7.2MHz Supports software switching (Initial cycle time is 1.33s) * Halt mode : The microcontroller operating clock is stopped in Halt mode. There are four conditions that can clear Halt mode : Interrupt requests, timer flip-flop overflows, port PA inputs, and HOLD pin inputs. * Operating supply voltage : 4.5 to 5.5V (Microcontroller block only : 3.5 to 5.5V) * Package : QIP100E * OTP version : LC72F3781 * Development tools : Emulator : RE128V Evaluation chip : LC72EV3780 Evaluation board : EB-72EV3780 * Interrupt nesting levels
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Specifications
Absolute Maximum Ratings at Ta = 25C VSS = 0V
Parameter Maximum supply voltage Input voltage Symbol VDD max VIN1 VIN2 Output voltage VOUT1 VOUT2 VOUT3 Output current IOUT1 IOUT2 Allowable power dissipation Operating temperature Storage temperature Pd max Topr Tstg PC-PORT All input pins other than VIN1 PJ-PORT PC-PORT All input pins other than VOUT1 and VOUT2 PC, PJ-PORT PB, PD, PE, PF, PG, PK, PL, PM, PN, PO, PP PQ, PR, PS, PT-PORT, EO1, EO2, SUBPD Ta = -40 to +85 C Conditions Ratings -0.3 to +6.5 -0.3 to +8 -0.3 to VDD+0.3 -0.3 to +14 -0.3 to +8 -0.3 to VDD+0.3 0 to +5 0 to +3 400 -40 to +85 -40 to +125 Unit V V V V V V mA mA mW C C
Allowable Operating Range at Ta = -40 to +85C, VDD = 3.5 to 5.5V
Parameter Supply voltage Symbol VDD1 VDD2 VDD3 Input high-level voltage VIH2 VIH3 VIH4 Input low-level voltage VIL1 VIH1 CPU and PLL operation CPU operation Memory retention PB, PC, PH, PI, PL, PM, PN, PP, PO, PQ, PR, PS, PT-PORT, HCTR, LCTR, INEO, SUBPD (with the I/O ports set to input mode) PD, PE, PF, PG, PK-PORT, LCTR (in period measurement mode), HOLD, RESET SNS PA-PORT PB, PC, PH, PI, PL, PM, PN, PP, PO, PQ, PR, PS, PT-PORT, HCTR, LCTR, INEO, SUBPD (with the I/O ports set to input mode) VIL2 VIL3 VIL4 Input frequency FIN1 FIN2 FIN3 FIN4 FIN5 FIN6 FIN7 FIN8 Input amplitude VIN1 VIN2 VIN3 Input voltage range VIN6 PA, PD, PE, PF, PG, PK-PORT, LCTR (in period measurement mode), RESET SNS HOLD XIN FMIN : VIN2, VDD1 FMIN : VIN3, VDD1 AMIN(H) : VIN3, VDD1 AMIN(L) : VIN3, VDD1 HCTR : VIN3, VDD1 LCTR : VIN3, VDD1 LCTR (in period measurement) : VIH2, VIL2, VDD1 XIN FMIN FMIN, AMIN, HCTR, LCTR ADI0 to ADI7 0 0 0 4.0 10 10 2.0 0.5 0.4 100 1 0.5 0.07 0.04 0 4.5 0.2VDD 1.1 0.4VDD 8.0 150 130 40 10 12 500 20x10
3
Pins min 4.5 3.5 1.1 0.7VDD
Ratings typ 5.0 mx 5.5 5.5 5.5 VDD
uit
V
V
0.8VDD 2.5 0.6VDD 0
VDD VDD VDD 0.3VDD
V V V V
V V V MHz MHz MHz MHz MHz MHz kHz Hz Vrms Vrms Vrms V
1.5 1.5 1.5 VDD
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Electrical Characteristics in the allowable operating ranges
Parameter Input high-level current Symbol IIH1 IIH2 IIH3 XIN : VI = VDD = 5.0V FMIN, AMIN, HCTR, LCTR : VI = VDD = 5.0V PA, PB, PC, PD, PE, PF, PG, PH, PI, PK, PL, PM, PN, PO, PP, PQ, PR, PS, PT-PORT, SNS, HOLD, RESET, HCTR, LCTR, INEO, SUBPD : VI = VDD = 5.0V (with the ports PB, PC, PD, PE, PF, PG, PK, PL, PM, PN, PP, PO, PQ, PR, PS, and PT-PORT set to input mode) Input low-level current IIL1 IIL2 IIL3 XIN : VI = VDD = VSS FMIN, AMIN, HCTR, LCTR : VI = VDD = VSS PA, PB, PC, PD, PE, PF, PG, PH, PI, PK, PL, PM, PN, PO, PP, PQ, PR, PS, PT-PORT, SNS, HOLD, RESET, HCTR, LCTR, INEO, SUBPD : VI = VSS (with the ports PB, PC, PD, PE, PF, PG, PK, PL, PM, PN, PP, PO, PQ, PR, PS, and PT-PORT set to input mode) Hysteresis Output high-level voltage VH VOH1 VOH2 VOH3 Output low-level voltage VOL1 VOL2 VOL3 VOL4 Output off leakage current IOFF2 IOFF3 A/D conversion error Rejected pulse width Power down detection voltage Power supply current IDD1 IDD2 IDD3 IDD4 IDD5 IDD6 VDD1 : FIN2 = 130MHz Ta = 25C, X'tal : 4.5MHz VDD1 : FIN2 = 130MHz Ta = 25C, X'tal : 7.2MHz VDD2 : Halt mode Ta = 25C, X'tal : 4.5 MHz VDD2 : Halt mode Ta = 25C, X'tal : 7.2MHz Backup mode (OSC stopped) VDD = 5.5V, Ta = 25C Backup mode (OSC stopped) VDD = 2.5V, Ta = 25C *2 (Fig. 2) *2 (Fig. 2) *1 (Fig. 1) PREJ1 VDET IOFF1 PD, PE, PF, PG, PK-PORT, RESET, LCTR (in period measurement) PB, PD, PE, PF, PG, PK, PL, PM, PN, PO, PP, PQ, PR, PS, PT-PORT : IO = -1mA EO1, EO2, SUBPD : IO = -500A XOUT : IO = -200A PB, PD, PE, PF, PG, PK, PL, PM, PN, PO, PP PQ, PR, PS, PT-PORT : IO = -1mA EO1, EO2, SUBPD : IO = -500A XOUT : IO = -200A PC, PJ-PORT : IO = -5mA PB, PD, PE, PF, PG, PK, PL, PM, PN, PO, PP, PQ, PR, PS, PT-PORT EO1, EO2, SUBPD PC, PJ-PORT ADI0 to ADI7 SNS 2.7 3.0 5 5.5 0.45 0.55 5 1 -3 -100 -5 -1.5 0.1VDD VDD-1.0 VDD-1.0 VDD-1.0 1.0 1.0 1.5 2.0 3 100 5 +1.5 50 3.3 10 11 0.2VDD V V V V V V V V A nA A LSB s V mA mA mA mA A A 3 A 2.0 4.0 5.0 10 15 30 A A 3 A Pins min 2.0 4.0 Ratings typ 5.0 10 max 15 30 A A unit
*1 : Twenty instruction steps are executed every millisecond. The PLL, universal counter, and other functions are stopped.
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Test Circuits
Figure 1. IDD2 in Halt Mode
Figure 2. IDD3 and IDD4 in Backup Mode
Package Dimensions
unit : mm 3151A
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Pin Assignment
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Block Diagram
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Pin Description
Pin name PA0 PA1 PA2 PA3 Pin No. 32 31 30 29 I/O I Dedicated input ports. These ports are designed with a low threshold voltage. Input is disabled in Backup mode. Pin explanation Equivalent circuit
PB0 PB1 PB2 PB3
28 27 26 25
I/O
General-purpose I/O ports. The mode (input or output) is set using the IOS2 instruction. Input is disabled and the pins go to the high-impedance state in Backup mode. These ports are set up as general-purpose input ports after a power on reset.
PC0 PC1 PC2 PC3
24 23 22 21
I/O
General-purpose I/O ports (middle-voltage input and output). The mode (input or output) is set using the IOS2 instruction. External pull-up resistors are required since the output circuits are open drain. Input is disabled and the pins go to the high-impedance state in Backup mode. These ports are set up as general-purpose input ports after a power on reset.
PD0/INT4 PD1/INT5 PD2 PD3
20 19 18 17
I/O
General-purpose I/O and external interrupt shared function ports. The input formats are Schmitt inputs. The external interrupt function is enabled when the external interrupt enable flag is set. * When used as general-purpose I/O ports : The mode (input or output) is set in 1-bit units using the IOS2 instruction. * When used as external interrupt pins : The external interrupt functions are enabled by setting the corresponding external interrupt enable flag (INT4EN or INT5EN). In this case, the pins must be set to input mode in advance. Input is disabled and the pins go to the high-impedance state in Backup mode. These ports are set up as general-purpose input ports after a power on reset.
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Pin name PE0 PE1/SCK2 PE2/SO2 PE3/SI2 PF0 PF1/SCK1 PF2/SO1 PF3/SI1 PG0 PG1/SCK0 PG2/SO0 PG3/SI0 Pin No. 16 15 14 13 12 11 10 9 8 7 6 5 I/O I/O Pin explanation General-purpose I/O ports with shared functions as serial I/O ports. The input formats are Schmitt inputs. The PE1/SCK2 and PE2/SO2 pins can be switched to function as open drain outputs. The IOS1 instruction is used to switch between the general-purpose I/O port and serial I/O port functions. * When used as general-purpose I/O ports : The pins are set to the general-purpose I/O port function using the IOS1 instruction. The mode (input or output) is set in 1-bit units using the IOS1 instruction * When used serial I/O ports : The pins are set to the serial I/O port function using the IOS1 instruction. [Pin states when set to the serial I/O port function] PE0, PF0, PG0 ... General-purpose I/O PE1, PF1, PG1 ... SCK input or output PE2, PF2, PG2 ... SO output PE3, PF3, PG3 ... SI input The PE1/SCK2 and PE2/SO2 pins can be switched to function as open drain outputs with the IOS2 instruction. When using this circuit type, the external pull-up resistors must be connected to the same power supply as that used by the IC. Input is disabled and the pins go to the high-impedance state in Backup mode. These ports are set up as general-purpose input ports after a power on reset. XIN XOUT 1 100 I O Connections for 4.5MHz/7.2MHz crystal oscillator element Equivalent circuit
EO1 EO2
98 97
O
Main charge pump outputs. These pins output a high level when the frequency of the local oscillator divided by n is higher than that of the reference frequency, and they output a low level when that frequency is lower. They go to the high-impedance state when the frequencies match. These pins go to the high-impedance state in Backup mode, after a power on reset, and in the PLL stopped state.
VDDPORT VDDPLL VSSCPU VSSPORT VSSADC VSSPLL
39 93 4 40 81 96
-
Power supply connections. The VDDPORT and VSSPORT pins are mainly supply power for the peripheral I/O blocks. The VDDPLL and VSSPLL pins are mainly for the PLL circuits and the regulator. The VSSCPU pin is mainly used by the CPU block. The VSSADC pin is mainly used by the ADC block. Since all the VDD and VSS pins are independent, all must be connected to the same power supply.
VREG
3
O
Internal low voltage output. Connect a bypass capacitor to this pin.
Continued on next page.
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Pin name FMIN Pin No. 95 I/O I Pin explanation FM VCO (local oscillator) input. This pin is selected with CW1 in the PLL instruction. The signal input to this pin must be capacitor coupled. Input is disabled in Backup mode, after a power on reset, and in the PLL stopped state. AMIN 94 I AM VCO (local oscillator) input. This pin is selected and the band set with CW1 (b1, b0) in the PLL instruction. b1 1 1 b0 0 1 Band 2 to 40MHz (SW, AM upconversion) 0.5 to 10MHz (MW, LW) Equivalent circuit
The signal input to this pin must be capacitor coupled. Input is disabled in Backup mode, after a power on reset, and in the PLL stopped state. SUBPD 92 I/O Sub-charge pump output and general-purpose input shared function port. The IOS2 instruction is used for switching between the sub-charge pump output and general-purpose input functions. * When used as the sub-charge pump output : The sub-charge pump output function is set up with the IOS2 instruction. A high-speed locking circuit can be formed by using this pin in conjunction with the main charge pump. The sub-charge pump is controlled using the DZC instruction. b3 0 0 1 1 b2 0 1 0 1 High impedance Only operates when the PLL is unlocked (450kHz) Only operates when the PLL is unlocked (900kHz) Normal operation Operation
* When used as a general-purpose input : The general-purpose input function is set up with the IOS2 instruction. Data is read from the port using the INR instruction. This pin goes to the high-impedance state in Backup mode, after a power on reset, and in the PLL stopped state. INEO 91 I Dedicated input port. Data is read from the port using the INR instruction Input is disabled in Backup mode.
Continued on next page.
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Pin name HCTR Pin No. 90 I/O I Pin explanation Universal counter and general-purpose input shared function input port. The IOS1 instruction is used for switching between the universal counter and general- purpose input functions. * When used for frequency measurement : The universal counter function is set up with the IOS1 instruction. The counter is controlled using UCS and UCC instructions. Since this pin functions as an AC amplifier in this mode, the input signal must be input with capacitor coupling. * When used as a general-purpose input pin : The general-purpose input function is set up with the IOS1 instruction. Data is read from the port using the INR (b0) instruction. Input is disabled in Backup mode. (The input pin will be pulled down.) The universal counter function is selected after a power on reset. LCTR 89 I Universal counter (frequency or period measurement) and generalpurpose input shared function input port. The IOS1 instruction is used for switching between the universal counter and general-purpose input functions. * When used for frequency measurement : The universal counter function is set up with the IOS1 instruction. Set up LCTR frequency measurement mode with the UCS instruction, and control operation with the UCC instruction. Since this pin functions as an AC amplifier in this mode, the input signal must be input with capacitor coupling. * When used for period measurement : The universal counter function is set up with the IOS1 instruction. Set up LCTR frequency measurement mode with the UCS instruction, and control operation with the UCC instruction. Since the bias feedback resistor is disconnected in this mode, the input signal must be input with DC coupling. * When used as a general-purpose input pin : The general-purpose input port function is set up with the IOS1 instruction. Data is read from the port using the INR (b1) instruction. Input is disabled in Backup mode. (The input pin will be pulled down.) The universal counter function (HCTR frequency measurement mode) is selected after a power on reset. SNS 88 I Voltage sense and general-purpose input shared function port. This input circuit is designed with a low input threshold voltage. * When used as a voltage sense input : The pin is used to test for power failures on the return from Backup mode. Application can test this condition using the internal SNS flip-flop. The SNS flip-flop can be tested with the TST instruction. (This usage requires external components, capacitors and resistors. For the sample application circuit, see the user's manual.) * When used as a general-purpose input port : When used as a general-purpose input port the pin state can be tested with the TST instruction. Unlike the other input ports, input to this pin is not disabled in Backup mode and after a power on reset. As a result, through currents must be taken into account when designing applications that use this pin as a general-purpose input. HOLD 87 I Power supply monitor (with interrupt function) This is designed with a high input threshold voltage. This pin is normally connected to the ACC line and used for power off detection. When a power off state is detected, the HOLDON flag and the hold interrupt request flag will be set. To enter Backup mode, execute a CKSTP instruction when the HOLD pin is low. Set this pin high to clear Backup mode. Equivalent circuit
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Pin name RESET Pin No. 86 I/O I System reset pin. When the CPU is operating or in Halt mode, the system is reset when this pin is held low for at least one machine cycle. Execution starts with the PC pointing to location 0. At this time the SNS flip-flop is set. A low level must be applied for at least 50ms when power is first applied. PH0/ADI0 PH1/ADI1 PH2/ADI2 PH3/ADI3 PI0/ADI4 PI1/ADI5 PI2/ADI6 PI3/ADI7 85 84 83 82 81 80 79 78 I General-purpose input and A/D converter input shared function ports. The IOS1 instruction is used to switch between the general-purpose input and the A/D converter input functions. * When used as general-purpose input ports : The general-purpose input port function is set up with the IOS1 instruction. (In bit units) * When used as A/D converter input pins : The A/D converter input port function is set up with the IOS1 instruction. (In bit units) The pin whose voltage is to be converted is specified with the IOS1 instruction, and the conversion is started with UCC instruction. Note : Since input is disabled for ports specified for the ADI function, executing an input instruction for such a port will always return a low level. Input is disabled in Backup mode. These ports are set up as general-purpose input ports after a power on reset. PJ0 PJ1 PJ2 PJ3 76 75 74 73 O General-purpose output ports (high-voltage output) Since these are open-drain output circuits, external pull-up resistors are required. The internal transistors are turned off (resulting in a high-level output) in Backup mode and after a power on reset. PK0/INT0 PK1/INT1 PK2/INT2 PK3/INT3 72 71 70 69 I/O General-purpose I/O and external interrupt shared function ports. The input formats are Schmitt inputs. The external interrupt function is enabled when the external interrupt enable flag is set. * When used as general-purpose I/O ports : The mode (input or output) is set in 1-bit units using the IOS1 instruction. * When used as external interrupt pins : The external interrupt functions are enabled by setting the corresponding external interrupt enable flag (INT0EN through INT3EN). Here, the pins must be set to input mode in advance. Input is disabled and the pins go to the high-impedance state in Backup mode. These ports are set up as general-purpose input ports after a power on reset. Pin explanation Equivalent circuit
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Pin name PL0 to 3 PM0 to 3 Pin No. 68 to 61 I/O I/O General-purpose I/O ports The mode is switched between input and output with the IOS instruction. Input is disabled and the pins go to the high-impedance state in Backup mode. These ports are set up as general-purpose input ports after a power on reset. PN0/BEEP PN1 PN2 PN3 60 59 58 57 I/O General-purpose I/O port and beep tone output shared function ports. The IOS2 instruction is used to switch between the general-purpose I/O port and the beep tone output functions. * When used as general-purpose I/O ports : The general-purpose I/O port function is set up with the IOS2 instruction. (Pins PN1 through PN3 are dedicated general-purpose output pins.) * When used as the beep tone output pin : The beep tone output function is set up with the IOS2 instruction. The frequency is set up with the BEEP instruction. When this pin is used as the beep tone output pin, executing an output instruction for this pin only sets the internal latch and has no influence on the output. Input is disabled and the pins go to the high-impedance state in Backup mode. These ports are set up as general-purpose input ports after a power on reset. PO0 to 3 PP0 to 3 56 to 49 I/O General-purpose I/O ports The mode is switched between input and output with the IOS instruction. Input is disabled and the pins go to the high-impedance state in Backup mode. These ports are set up as general-purpose input ports after a power on reset. PQ0 to 3 PR0 to 3 PS0 to 3 PT0 to 3 48 to 41 38 to 33 I/O General-purpose I/O ports. The mode is switched between input and output with the IOS instruction, and data is input with the INR instruction and output with the OUTR instruction. The SPB, RPB, TPT, and TPF instruction cannot be used with these ports. Input is disabled and the pins go to the high-impedance state in Backup mode. These ports are set up as general-purpose input ports after a power on reset. TEST1 TEST2 99 2 LSI test pins. These pins must be connected to GND. Pin explanation Equivalent circuit
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Specifications of any and all SANYO Semiconductor products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Semiconductor Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor products (including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Semiconductor Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO Semiconductor believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of February, 2006. Specifications and information herein are subject to change without notice. PS No.8011-14/14

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